On March 23, 2016 a certificate of registration of copyright under number 64214 was issued to assistant professor Yaskevich V., graduate student Tikhonov E. and 3-rd year student Yaskevich Y. for developing a computer program to minimize logic functions using Veitch diagrams.

This program allows students to facilitate the study of important topics on minimizing logic functions.

This topic is studied in many disciplines, "Computers and microprocessors", "Architecture of computers", "Сomputer discrete mathematics" and others. One of the main tasks is designing complex circuits digital devices. When designing combinational circuits have to solve problems that relate to analysis and synthesis.

Synthesis of combinational circuits involves the construction of the block diagram of the device. Definition of logic elements and connections between them, which provide converting incoming digital signals to output signals. During synthesis is usually performed minimizing hardware costs of the device.

The program is a Windows application created in C++ using Visual Studio. In future it is planned to create a cross-platform application as a Web-based applications in Visual Studio language C#.